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datasheet real-time clock with serial i 2 c interface IDT1339 idt? real-time clock with serial i 2 c interface 1 IDT1339 rev k 032910 general description the IDT1339 serial real-time clock (rtc) is a low-p ower clock/date device with two programmable time-of-day alarms and a programmable square-wave output. addre ss and data are transferred serially through an i 2 c bus. the clock/date provides seconds, minutes, hours, day, d ate, month, and year information. the date at the end of the month is automatically adjusted for months with few er than 31 days, including corrections for leap year. the c lock operates in either the 24-hour or 12-hour format wi th am/pm indicator. the IDT1339 has a built-in power-s ense circuit that detects power failures and automatical ly switches to the backup supply, maintaining time, da te, and alarm operation. applications ? handhelds (gps, pos terminals) ? consumer electronics (set-top box, digital recordin g, network applications) ? office (fax/printers, copiers) ? medical (glucometer, medicine dispensers) ? telecomm (routers, switches, servers) ? other (thermostats, vending machines, modems, utili ty meters) features ? real-time clock (rtc) counts seconds, minutes, hour s, day, date, month, and year with leap-year compensat ion valid up to 2100 ? packaged in 8-pin msop, 8-pin soic, or 16-pin soic (surface-mount package with an integrated crystal) ? fast mode i 2 c serial interface ? two time-of-day alarms ? programmable square-wave output ? oscillator stop flag ? automatic power-fail detect and switch circuitry ? trickle-charge capability ? industrial temperature range (-40 to +85c) block diagram vcc gnd v backup scl sda crystal inside package for 16-pin soic only x1 x2 1 hz/4.096 khz/ 8.192 khz/32.768 khz sqw/int power control i 2 c interface 32.768 khz oscillator and divider control logic mux/ buffer clock, calendar counter 1 byte control 7 bytes buffer trickle charger byte 7 bytes alarm trickle charger 1 byte status
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 2 IDT1339 rev k 032910 pin assignment (8-pin msop/8-pin soic) pin assignment (16-pin soic) pin descriptions x1 scl sqw/int gnd vcc 12 3 4 87 6 5 sda x2 v backup idt 1339 16 1 15 2 14 3 13 4 5 6 7 8 9 10 12 11 scl vcc nc nc nc nc nc nc nc nc nc nc sda gnd sqw/int v backup idt 1339c pin number pin name pin description/function msop soic 1 ? x1 connections for standard 32.768 khz quartz crys tal. the internal oscillator circuitry is designed for operation with a crystal having a spec ified load capacitance (cl) of 7 pf. an external 32.768 khz oscillator can also drive the i dt1339. in this configuration, the x1 pin is connected to the external oscillator signal and the x2 pin is left floating. 2 ? x2 3 14 v backup backup supply input. supply voltage must be held be tween 1.3 v and 3.7 v for proper operation. this pin can be connected to a primary c ell, such as a lithium button cell. additionally, this pin can be connected to a rechar geable cell or a super cap that can be charged using the trickle charger circuit. diodes p laced in series between the backup source and the vbat pin may prevent proper operatio n. if a backup supply is not required, vbat must be connected to ground. 4 15 gnd connect to ground. dc power is provided to th e device on these pins. 5 16 sda serial data input/output. sda is the input/ou tput pin for the i 2 c serial interface. the sda pin is an open-drain output and requires an external pu ll-up resistor (2 k typical). 6 1 scl serial clock input. scl is used to synchronize data movement on the serial interface. it is an open-drain output and requires an external pull-up resistor (2 k typical). 7 2 sqw/int square-wave/interrupt output. programmable square-w ave or interrupt output signal. the sqw/int pin is an open-drain output and requires an extern al pull-up resistor (10 k typical). 8 3 v cc primary power supply. when voltage is applied withi n normal limits, the device is fully accessible and data can be written and read. ? 4 - 13 nc no connect. these pins are unused and must be connected to ground.
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 3 IDT1339 rev k 032910 typical operating circuit detailed description the following sections discuss in detail the oscill ator block, power control block, clock/calendar register, alarm s, trickle charger, and serial i 2 c block. oscillator block selection of the right crystal, correct load capaci tance and careful pcb layout are important for a stable cryst al oscillator. due to the optimization for the lowest possible current in the design for these oscillators, losses caused by parasitic currents can have a significant impact on the overall oscillator performance. extra care needs to be taken to maintain a certain quality and cleanliness of th e pcb. crystal selection the key parameters when selecting a 32 khz crystal to work with IDT1339 rtc are: ? recommended load capacitance ? crystal effective series resistance (esr) ? frequency tolerance effective load capacitance please see diagram below for effective load capacit ance calculation. the effective load capacitance (cl) sh ould match the recommended load capacitance of the cryst al in order for the crystal to oscillate at its specified parallel resonant frequency with 0ppm frequency error. in the above figure, x1 and x2 are the crystal pins of our device. cin1 and cin2 are the internal capacitors w hich include the x1 and x2 pin capacitance. cex1 and cex 2 are the external capacitors that are needed to tune the crystal frequency. ct1 and ct2 are the pcb trace capacitanc es between the crystal and the device pins. cs is the shunt capacitance of the crystal (as specified in the cry stal manufacturer's datasheet or measured using a networ k analyzer). note : IDT1339csri integrates a standard 32.768 khz (20ppm) crystal in the package and contributes an additional frequency error of 10ppm at nominal v cc (+3.3 v) and t a = +25c. cpu x1 x2 v cc sqw/int v backup gnd sda scl crystal IDT1339 + - v cc r pu 2k v cc v cc 10k r pu 2k 1 2 6 5 73 4 8
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 4 IDT1339 rev k 032910 esr (effective series resistance) choose the crystal with lower esr. a low esr helps the crystal to start up and stabilize to the correct ou tput frequency faster compared to high esr crystals. frequency tolerance the frequency tolerance for 32 khz crystals should be specified at nominal temperature (+25c) on the cry stal manufacturer datasheet. the crystals used with idt1 338 typically have a frequency tolerance of 20ppm at + 25c. specifications for a typical 32 khz crystal used wi th our device are shown in the table below. pcb design consideration ? signal traces between idt device pins and the cryst al must be kept as short as possible. this minimizes parasitic capacitance and sensitivity to crosstalk and emi. note that the trace capacitances play a role i n the effective crystal load capacitance calculation. ? data lines and frequently switching signal lines sh ould be routed as far away from the crystal connections as possible. crosstalk from these signals may disturb the oscillator signal. ? reduce the parasitic capacitance between x1 and x2 signals by routing them as far apart as possible. ? the oscillation loop current flows between the crys tal and the load capacitors. this signal path (crystal to c l1 to cl2 to crystal) should be kept as short as possible and ideally be symmetric. the ground connections for bo th capacitors should be as close together as possible. never route the ground connection between the capacitors all around the crystal, because this lon g ground trace is sensitive to crosstalk and emi. ? to reduce the radiation / coupling from oscillator circuit, an isolated ground island on the gnd layer could be made. this ground island can be connected at one po int to the gnd layer. this helps to keep noise generate d by the oscillator circuit locally on this separated is land. the ground connections for the load capacitors and the oscillator should be connected to this island. pcb layout pcb assembly, soldering and cleaning board-assembly production process and assembly qual ity can affect the performance of the 32 khz oscillator . depending on the flux material used, the soldering process can leave critical residues on the pcb surface. hig h humidity and fast temperature cycles that cause hum idity condensation on the printed circuit board can creat e process residuals. these process residuals cause th e insulation of the sensitive oscillator signal lines towards each other and neighboring signals on the pcb to de crease. high humidity can lead to moisture condensation on the surface of the pcb and, together with process resid uals, reduce the surface resistivity of the board. flux r esiduals on the board can cause leakage current paths, especial ly in humid environments. thorough pcb cleaning is theref ore highly recommended in order to achieve maximum performance by removing flux residuals from the boa rd after assembly. in general, reduction of losses in the os cillator circuit leads to better safety margin and reliabili ty. power control the power-control function is provided by a precise , temperature-compensated voltage reference and a comparator circuit that monitors the v cc level. the device is fully accessible and data can be written and read w hen v cc is greater than v pf . however, when v cc falls below v pf , the internal clock registers are blocked from any acces s. if v pf is less than v backup , the device power is switched from v cc to v backup when v cc drops below v pf . if v pf is greater than v backup , the device power is switched from v cc to v backup when v cc drops below v backup . the registers are maintained from the v backup source until v cc is returned to nominal levels (table 1). after v cc returns above v pf , read and write access is allowed after t rec (see the ?power-up/down timing? diagram). parameter symbol min typ max units nominal freq. f o 32.768 khz series resistance esr 50 k load capacitance c l 7 pf 1339
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 5 IDT1339 rev k 032910 table 1. power control power-up/down timing table 2. power-up/down characteristics ambient temperature -40 to +85 c note: this delay applies only if the oscillator is runni ng. if the oscillator is disabled or stopped, no po wer-up delay occurs. supply condition read/write access powered by v cc < v pf , v cc < v backup no v backup v cc < v pf , v cc > v backup no v cc v cc > v pf , v cc < v backup yes v cc v cc > v pf , v cc > v backup yes v cc parameter symbol conditions min. typ. max. units recovery at power-up t rec (see note below) 2 ms v cc fall time; v pf(max) to v pf(min) t vccf 300 s v cc rise time; v pf(min) to v pf(max) t vccr 0 s
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 6 IDT1339 rev k 032910 address map table 3 (timekeeper registers) shows the address ma p for the IDT1339 registers. during a multibyte acc ess, when the address pointer reaches the end of the register spa ce (10h), it wraps around to location 00h. on an i 2 c start, stop, or address pointer incrementing to location 00h, the c urrent time is transferred to a second set of regis ters. the time information is read from these secondary registers, while the clock may continue to run. this eliminat es the need to re-read the registers in case of an update of the main regi sters during a read. table 3. timekeeper registers note : unless otherwise specified, the state of the regi sters are not defined when power is first applied o r when v cc and v backup falls below the v backup(min) . address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 func tion range 00h 0 10 seconds seconds seconds 00 - 59 01h 0 10 minutes minutes minutes 00 - 59 02h 0 12/24 am /pm 10 hour hour hours 1 - 12 + am/pm 00 - 23 10 hour 03h 0 0 0 0 0 day day 1 - 7 04h 0 0 10 date date date 01 - 31 05h century 0 0 10 month month month/century 01 - 12 + century 06h 10 year year year 00 - 99 07h a1m1 10 seconds seconds alarm 1 seconds 00 - 59 08h a1m2 10 minutes minutes alarm 1 minutes 00 - 59 09h a1m3 12/24 am /pm 10 hour hour alarm 1 hours 1 - 12 + am/pm 00 - 23 10 hour 0ah a1m4 dy/dt 10 date day, date alarm 1 day, alarm 1 date 1 - 7, 1 - 31 0bh a2m2 10 minutes minutes alarm 2 minutes 00 - 59 0ch a2m3 12/24 am /pm 10 hour hour alarm 2 hours 1 - 12 + am/pm 00 - 23 10 hour 0dh a2m4 dy/dt 10 date day, date alarm 2 day, alarm 2 date 1 - 7, 1 - 31 0eh eosc 0 bbsqi rs2 rs1 intcn a2ie a1ie control 0fh osf 0 0 0 0 0 a2f a1f status 10h tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 trickle charger
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 7 IDT1339 rev k 032910 time and date operation the time and date information is obtained by readin g the appropriate register bytes. table 3 shows the rtc r egisters. the time and date are set or initialized by writing the appropriate register bytes. the contents of the tim e and date registers are in the bcd format. the IDT1339 c an be run in either 12-hour or 24-hour mode. bit 6 of the hours register is defined as the 12- or 24-hour mode-sele ct bit. when high, the 12-hour mode is selected. in the 12- hour mode, bit 5 is the am /pm bit with logic high being pm. in the 24-hour mode, bit 5 is the second 10-hour bit (20 t o 23 hours). all hours values, including the alarms, mus t be re-entered whenever the 12/24 -hour mode bit is changed. the century bit (bit 7 of the month register) is to ggled when the years register overflows from 99 to 00. the day -of-week register increments at midnight. values that corres pond to the day of week are user-defined, but must be seque ntial (i.e., if 1 equals sunday, then 2 equals monday and so on). illogical time and date entries result in undefined operation. when reading or writing the time and date registers , secondary (user) buffers are used to prevent errors when the internal registers update. when reading the tim e and date registers, the user buffers are synchronized t o the internal registers on any start or stop, and when t he address pointer rolls over to zero. the countdown chain is reset whenever the seconds register is written. write tra nsfers occurs on the acknowledge pulse from the device. to avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written w ithin one second. if enabled, the 1 hz square-wave output tra nsitions high 500 ms after the seconds data transfer, provid ed the oscillator is already running. alarms the IDT1339 contains two time of day/date alarms. a larm 1 can be set by writing to registers 07h to 0ah. alar m 2 can be set by writing to registers 0bh to 0dh. the alarms can be programmed (by the alarm enable and intcn bits of t he control register) to activate the sqw/int output on an alarm match condition. bit 7 of each of the time of day/date alarm registers are mask bits (table 4). when all t he mask bits for each alarm are logic 0, an alarm only occu rs when the values in the timekeeping registers 00h to 06h match the values stored in the time of day/date alarm registe rs. the alarms can also be programmed to repeat every secon d, minute, hour, day, or date. table 4 shows the possi ble settings. configurations not listed in the table re sult in illogical operation. the dy/dt bits (bit 6 of the alarm day/date registers) contr ol whether the alarm value stored in bits 0 to 5 of th at register reflects the day of the week or the date of the mon th. if dy/dt is written to a logic 0, the alarm is the result o f a match with date of the month. if dy/dt is written to a logic 1, the alarm is the result of a match with day of t he week. the device checks for an alarm match once per secon d. when the rtc register values match alarm register settings, the corresponding alarm flag ?a1f? or ?a2 f? bit is set to logic 1. if the corresponding alarm interrup t enable ?a1ie? or ?a2ie? is also set to logic 1 and the int cn bit is set to logic 1, the alarm condition activates the sqw/i nt signal. if the bbsqi bit is set to 1, the int output activates while the part is being powered by v backup . the alarm output remains active until the alarm flag is cleared by t he user.
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 8 IDT1339 rev k 032910 table 4. alarm mask bits special-purpose registers the IDT1339 has two additional registers (control a nd status) that control the rtc, alarms, and square -wave output. control register (0eh) bit 7: enable oscillator (eosc ). this bit when set to logic 0 starts the oscillator . when this bit is set to a logic 1, the oscillator is stopped. this bit is enabled (log ic 0) when power is first applied. bit 5: battery-backed square-wave and interrupt ena ble (bbsqi). this bit when set to a logic 1 enables the square wave or interrupt output when v cc is absent and the IDT1339 is being powered by the v backup pin. when bbsqi is a logic 0, the sqw/int pin goes high impedance when v cc falls below the power-fail trip point. this bit is disabled (logic 0) when power is first applied. bits 4 and 3: rate select (rs2 and rs1). these bits control the frequency of the square-wav e output when the square wave has been enabled. table 5 shows the squ are-wave frequencies that can be selected with the rs bits. these bits are both set to logic 1 (32 khz) when po wer is first applied. dy/dt alarm 1 register mask bits (bit 7) alarm rate a1m4 a1m3 a1m2 a1m1 x 1 1 1 1 alarm once per second. x 1 1 1 0 alarm when seconds match. x 1 1 0 0 alarm when minutes and seconds match. x 1 0 0 0 alarm when hours, minutes, and seconds match. 0 0 0 0 0 alarm when date, hours, minutes, and seconds m atch. 1 0 0 0 0 alarm when day, hours, minutes, and seconds ma tch. dy/dt alarm 2 register mask bits (bit 7) alarm rate a2m4 a2m3 a2m2 x 1 1 1 alarm once per minute (00 sec. of every min.). x 1 1 0 alarm when minutes match. x 1 0 0 alarm when hours and minutes match. 0 0 0 0 alarm when date, hours, and minutes match. 1 0 0 0 alarm when day, hours, and minutes match. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eosc 0 bbsqi rs2 rs1 intcn a2ie a1ie
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 9 IDT1339 rev k 032910 table 5. sqw/int output bit 2: interrupt control (intcn). this bit controls the relationship between the two alarms and the interrupt output pins. when the intcn bit is set to logic 1, a match between the timekeeping registers and the alarm 1 or alarm 2 registers activate the sqw/int pin (provided that the alarm is enabled). when the intcn bit is set to logic 0, a square wave is output on the sqw/int pin. this bit is set to logic 0 when power is firs t applied. bit 1: alarm 2 interrupt enable (a2ie). when set to a logic 1, this bit permits the alarm 2 flag (a2f) bit in the status register to assert sqw/int (when intcn = 1). when the a2ie bit is set to logi c 0 or intcn is set to logic 0, the a2f bit does not initiate an interrupt signal. the a2ie bit is disabled (logic 0) when power is fi rst applied. bit 0: alarm 1 interrupt enable (a1ie). when set to logic 1, this bit permits the alarm 1 flag (a1f) bit in the status register to assert sqw/int (when intcn = 1). when the a1ie bit is set to logi c 0 or intcn is set to logic 0, the a1f bit does not initiate an interrupt signal. the a1ie bit is disabled (logic 0) when power is first appl ied. status register (0fh) bit 7: oscillator stop flag (osf). a logic 1 in this bit indicates that the oscillato r either is stopped or was stopped for some period of time and may be used to judge th e validity of the clock and date data. this bit is edge triggered and is set to logic 1 when the oscillator stops. th e following are examples of conditions that can cau se the osf bit to be set: 1) the first time power is applied. 2) the voltage on both v cc and v backup are insufficient to support oscillation. 3) the eosc bit is turned off. 4) external influences on the crystal (e.g., noise, leakage, etc.). this bit remains at logic 1 until written to logic 0. this bit can only be written to a logic 0. bit 1: alarm 2 flag (a2f). a logic 1 in the alarm 2 flag bit indicates that t he time matched the alarm 2 registers. if the a2ie bit is a logic 1 and the intcn bit is set to a logic 1, the sqw/int pin is also asserted. a2f is cleared when written to logic 0. this bit can only be written to logic 0. attempting to write to logic 1 leaves the value unchanged. bit 0: alarm 1 flag (a1f). a logic 1 in the alarm 1 flag bit indicates that t he time matched the alarm 1 registers. if the a1ie bit is a logic 1 and the intcn bit is set to a logic 1, the sqw/int pin is also asserted. a1f is cleared when written to logic 0. this bit can only be written to logic 0. attempting to write to logic 1 leaves the value unchanged. intcn rs2 rs1 sqw/int output a2ie a1ie 0 0 0 1 hz x x 0 0 1 4.096 khz x x 0 1 0 8.192 khz x x 0 1 1 32.768 khz x x 1 x x a1f 0 1 1 x x a2f 1 0 1 x x a2f + a1f 1 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 osf 0 0 0 0 0 a2f a1f
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 10 IDT1339 rev k 032910 trickle charger register (10h) programmable trickle charger the simplified ?programmable trickle charger? schem atic shows the basic components of the trickle char ger. the trickle-charge select (tcs) bits (bits 4 to 7) cont rol the selection of the trickle charger. to preven t accidental enabling, only a pattern of 1010 on the tcs bits enables the trick le charger. all other patterns disable the trickle charger. the trickle charger is disabled when power is first applied. th e diode-select (ds) bits (bits 2 and 3) select whet her or not a diode is connected between v cc and v backup . the rout bits (bits 0 and 1) select the value of the resistor connected between v cc and v backup . table 6 shows the bit values. table 6. trickle charger register (10h) warning: the rout value of 250 must not be selected whenever v cc is greater than 3.63 v. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout 1 rout 0 x x x x 0 0 x x disabled x x x x 1 1 x x disabled x x x x x x 0 0 disabled 1 0 1 0 0 1 0 1 no diode, 250 resistor 1 0 1 0 1 0 0 1 one diode, 250 resistor 1 0 1 0 0 1 1 0 no diode, 2k resistor 1 0 1 0 1 0 1 0 one diode, 2k resistor 1 0 1 0 0 1 1 1 no diode, 4k resistor 1 0 1 0 1 0 1 1 one diode, 4k resistor 0 0 0 0 0 0 0 0 initial power-up values
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 11 IDT1339 rev k 032910 the user determines diode and resistor selection ac cording to the maximum current desired for battery or super cap charging. the maximum charging current can be calcu lated as illustrated in the following example. assu me that a 3.3 v system power supply is applied to v cc and a super cap is connected to v backup . also assume that the trickle charger has been enabled with a diode and resistor r2 between v cc and v backup . the maximum current i max would therefore be calculated as follows: i max = (3.3 v - diode drop) / r2 (3.3 v - 0.7 v) / 2k 1.3 ma as the super cap or battery charges, the voltage dr op between v cc and v backup decreases and therefore the charge current decreases. i 2 c serial data bus the IDT1339 supports the i 2 c bus protocol. a device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. the device tha t controls the message is called a master. the devices that ar e controlled by the master are referred to as slaves. the bus must be controlled by a master device that generate s the serial clock (scl), controls the bus access, and ge nerates the start and stop conditions. the IDT1339 operates as a slave on the i 2 c bus. within the bus specifications, a standard mode (100 khz cycle rate) and a fast mode (400 khz cycle rate) are defined. the IDT1339 works in b oth modes. connections to the bus are made via the open -drain i/o lines sda and scl. the following bus protocol has been defined (see th e ?data transfer on i 2 c serial bus? figure): ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain sta ble whenever the clock line is high. changes in the dat a line while the clock line is high are interpreted as con trol signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line, from high to low, while the clock is high, defines a start condition. stop data transfer: a change in the state of the data line, from low to high, while the clock line is high, def ines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is sta ble for the duration of the high period of the clock signal. th e data on the line must be changed during the low period of t he clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condit ion and terminated with a stop condition. the number of dat a bytes transferred between start and stop conditions is not limited, and is determined by the master device . the information is transferred byte-wise and each recei ver acknowledges with a ninth bit. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the recept ion of each byte. the master device must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda l ine during the acknowledge clock pulse in such a way th at the sda line is stable low during the high period of th e acknowledge related clock pulse. of course, setup a nd hold times must be taken into account. a master must sig nal an end of data to the slave by not generating an ackno wledge bit on the last byte that has been clocked out of t he slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. timeout: timeout is where a slave device resets its interface whenever clock goes low for longer than t he timeout, which is typically 35msec. this added logi c deals with slave errors and recovering from those errors. when timeout occurs, the slave interface should re-initi alize itself and be ready to receive a communication from the ma ster, but it will expect a start prior to any new communi cation.
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 12 IDT1339 rev k 032910 data transfer on i 2 c serial bus depending upon the state of the r/w bit, two types of data transfer are possible: 1) data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each receive d byte. data is transferred with the most significant bit ( msb) first. 2) data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge b it. this is followed by the slave transmitting a number of d ata bytes. the master returns an acknowledge bit after all rec eived bytes other than the last byte. at the end of the l ast received byte, a ?not acknowledge? is returned. the master d evice generates all of the serial clock pulses and the st art and stop conditions. a transfer is ended with a stop co ndition or with a repeated start condition. since a repeate d start condition is also the beginning of the next s erial transfer, the bus is not released. data is transfer red with the most significant bit (msb) first. the IDT1339 can operate in the following two modes: 1) slave receiver mode (write mode): serial data and clock are received through sda and scl. after each byte is received an acknowledge bit is transmitted. start a nd stop conditions are recognized as the beginning and end of a serial transfer. address recognition is perfor med by hardware after reception of the slave address and d irection bit (see the ?data write?slave receiver mode? figur e). the slave address byte is the first byte received after the start condition is generated by the master. the slave add ress byte contains the 7-bit IDT1339 address, which is 1 101000, followed by the direction bit (r/w ), which is 0 for a write. after receiving and decoding the slave address byte the slave outputs an acknowledge on the sda line. after the IDT1339 acknowledges the slave address + write bit, the master transmits a register address to the IDT1339. this sets the register pointer on the IDT1339, with the IDT1339 acknowledging the transfer. the master may then tra nsmit zero or more bytes of data, with the IDT1339 acknow ledging each byte received. the address pointer increments after each data byte is transferred. the master generates a stop condition to terminate the data write. 2) slave transmitter mode (read mode): the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit indicates that the transfer direction is reversed. serial data is tran smitted on sda by the IDT1339 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer (see the ?da ta read?slave transmitter mode? figure). the slave add ress byte is the first byte received after the start con dition is generated by the master. the slave address byte con tains the 7-bit IDT1339 address, which is 1101000, follow ed by the direction bit (r/w ), which is 1 for a read. after receiving and decoding the slave address byte the slave outpu ts an acknowledge on the sda line. the IDT1339 then begin s to transmit data starting with the register address po inted to by
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 13 IDT1339 rev k 032910 the register pointer. if the register pointer is no t written to before the initiation of a read mode the first addr ess that is read is the last one stored in the register pointer . the address pointer is incremented after each byte is transferred. the IDT1339 must receive a ?not acknow ledge? to end a read. data write ? slave receiver mode data read (from current pointer location) ? slave t ransmitter mode data read (write pointer, then read) ? slave receiv e and transmit
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 14 IDT1339 rev k 032910 handling, pcb layout, and assembly the IDT1339 package contains a quartz tuning-fork c rystal. pick-and-place equipment may be used, but p recautions should be taken to ensure that excessive shocks are aviode d. ultarsonic cleaning equipment should be avioded to prevent damage to the crystal. avoid running signal traces under the package, unle ss a ground plane is placed between the package and the signal line. all nc (no connect) pins must be connected to groun d. moisture-sensitive packages are shipped from the fa ctory dry-packed. handling instructions listed on t he package label must be followed to prevent damage during reflow. refer to the ipc/jedec j-std-020 standard for moisture-se nsitive device (msd) classifications. absolute maximum ratings stresses above the ratings listed below can cause p ermanent damage to the IDT1339. these ratings, whic h are standard values for idt commercially rated parts, a re stress ratings only. functional operation of the device at these or any other conditions above those indicated in th e operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. el ectrical parameters are guaranteed only over the recommended operating temperature range. recommended dc operating conditions note a: operating voltages without a back up supply connec ted. item symbol rating all inputs and outputs -0.3 v to +6.0 v storage temperature -55 to +125 c soldering temperature 260 c parameter symbol min. typ. max. units ambient operating temperature t a -40 +85 c backup supply voltage v backup 1.3 3.0 3.7 v pull-up resistor voltage (sqw/int , sda, scl), v cc = 0v v pu 5.5 v logic 1 v ih 0.7 v cc v cc + 0.3 v logic 0 v il -0.3 0.3 v cc v supply voltage IDT1339-2, note a v cc v pf 2.0 5.5 v IDT1339-31, note a v pf 3.3 5.5 power fail voltage IDT1339-2, note b v pf 1.40 1.70 1.80 v IDT1339-31, note b 2.45 2.70 2.97
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 15 IDT1339 rev k 032910 note b: when a back up supply voltage is connected choose proper part number 1339-2 or 1339-31 depending upon the back up supply voltage.
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 16 IDT1339 rev k 032910 dc electrical characteristics unless stated otherwise, v cc = min to max , ambient temperature -40 to +85 c, note 1 dc electrical characteristics unless stated otherwise, v cc = 0v , ambient temperature -40 to +85 c, note 1 parameter symbol conditions min. typ. max. units input leakage i li note 2 1 a i/o leakage i lo note 3 1 a logic 0 out v cc > 2.0 v i ol IDT1339-2, note 3 3 ma logic 0 out vol = 0.4; vcc > vcc min. v cc > 2.0 v i ol IDT1339-31, note 3 3 ma logic 0 out vol = 0.2 v ( v cc ); 1.8 v < v cc < 2.0 v i ol note 3 3 ma logic 0 out vol = 0.2 v ( v cc ); 1.3 v < v cc < 1.8 v i ol note 3 250 a v cc active current i cca note 4 450 a v cc standby current, note 5 i ccs v cc < 3.63 v 80 150 a 3.63 v < v cc < 5.5 v 200 trickle-charger resistor register 10h = a5h, v cc = typ, v backup = 0v r1 note 6 250 trickle-charger resistor register 10h = a6h, v cc = typ, v backup = 0v r2 2000 trickle-charger resistor register 10h = a7h, v cc = typ, v backup = 0v r3 4000 v backup leakage current i bklkg 25 100 na parameter symbol conditions min. typ. max. units v backup current eosc = 0, sqw off i bkosc note 7 400 700 na v backup current eosc = 0, sqw on i bksqw note 7 600 1000 na v backup current eosc = 1 i bkdr note 7 10 100 na
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 17 IDT1339 rev k 032910 ac electrical characteristics unless stated otherwise, v cc = min to max , ambient temperature -40 to +85 c, note 13 warning: under no circumstances are negative unders hoots, of any amplitude, allowed when device is in battery-backup mode. note 1 : limits at -40c are guaranteed by design and are not production tested. note 2 : scl only. note 3 : sda and sqw/int . note 4 : i cca ?scl at f sc max, vil = 0.0v, vih = v cc , trickle charger disabled. note 5 : specified with the i 2 c bus inactive, vil = 0.0v, vih = v cc , trickle charger disabled. note 6 : v cc must be less than 3.63 v if the 250 resistor is selected. parameter symbol conditions min. typ. max. units scl clock frequency f scl fast mode 100 400 khz standard mode 100 bus free time between a stop and start condition t buf fast mode 1.3 s standard mode 4.7 hold time (repeated) start condition, note 8 t hd:sta fast mode 0.6 s standard mode 4.0 low period of scl clock t low fast mode 1.3 s standard mode 4.7 high period of scl clock t high fast mode 0.6 s standard mode 4.0 setup time for a repeated start condition t su:sta fast mode 0.6 s standard mode 4.7 data hold time, notes 9, 10 t hd:dat fast mode 0 0.9 s standard mode 0 data setup time, note 11 t su:dat fast mode 100 ns standard mode 250 rise time of both sda and scl signals, note 12 t r fast mode 20 + 0.1c b 300 ns standard mode 20 + 0.1c b 1000 fall time of both sda and scl signals, note 12 t f fast mode 20 + 0.1c b 300 ns standard mode 20 + 0.1c b 300 setup time for stop condition t su:sto fast mode 0.6 s standard mode 4.0 capacitive load for each bus line, note 12 c b 400 pf i/o capacitance (sda, scl) c i/o note 13 10 pf oscillator stop flag (osf) delay t osf note 14 100 ms
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 18 IDT1339 rev k 032910 note 7 : using recommended crystal on x1 and x2. note 8 : after this period, the first clock pulse is gener ated. note 9 : a device must internally provide a hold time of a t least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of t he falling edge of scl. note 10 : the maximum t hd:dat need only be met if the device does not stretch th e low period (t low ) of the scl signal. note 11 : a fast-mode device can be used in a standard-mode system, but the requirement t su:dat > to 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl s ignal. if such a device does stretch the low period of the scl sig nal, it must output the next data bit to the sda li ne t r(max) + t su:dat = 1000 + 250 = 1250 ns before the scl line is rele ased. note 12 : c b ?total capacitance of one bus line in pf. note 13 : guaranteed by design. not production tested. note 14 : the parameter t osf is the period of time the oscillator must be stopp ed for the osf flag to be set over the voltage range of 0.0v < v cc < v cc max and 1.3 v < v backup < 3.7 v. timing diagram
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 19 IDT1339 rev k 032910 typical operating characteristics (v cc =3.3v, t a =25 c) icc vs vcc (IDT1339-31) sda=gnd 0 4 8 12 16 20 2.7 3.2 3.7 4.2 4.7 5.2 supply current (ua) vcc (v) scl=400khz scl=0hz ibackup vs temperature (IDT1339-31) rs1=rs0=00 300 340 380 420 460 500 -40 -20 0 20 40 60 80 temperature (c) supply current (na) intc=1 intc=0 oscillator frequency vs supply voltage (IDT1339-31) 32768 32768.05 32768.1 2.8 3.3 3.8 4.3 4.8 5.3 frequency (hz) oscillator supply voltage (v) freq ibackup vs vbackup (IDT1339-31) rs1=rs0=00 380 385 390 395 400 405 410 415 420 425 1.3 1.8 2.3 2.8 3.3 vbackup (v) supply current (na) intc=1 intc=0
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 20 IDT1339 rev k 032910 thermal characteristics for 8msop thermal characteristics for 8soic thermal characteristics for 16soic parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 95 c/w thermal resistance junction to case jc 48 c/w parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 150 c/w ja 1 m/s air flow 140 c/w ja 3 m/s air flow 120 c/w thermal resistance junction to case jc 40 c/w parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 120 c/w ja 1 m/s air flow 115 c/w ja 3 m/s air flow 105 c/w thermal resistance junction to case jc 58 c/w
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 21 IDT1339 rev k 032910 marking diagram (8 msop) marking diagram (8 soic) notes: 1. ?#? is the lot number. 2. ?$? is the assembly mark code. 3. yyww is the last two digits of the year and week that the part was assembled. 4. ?g? denotes rohs compliant package. 5. ?i? denotes industrial grade. 6. bottom marking: country of origin if not usa. marking diagram (16 soic) 31gi yww$ IDT1339-31dvgi 92gi yww$ IDT1339-2dvgi IDT1339 -31dcgi #yyww$ 1 4 5 8 IDT1339-31dcgi IDT1339 -2dcgi #yyww$ 1 4 5 8 IDT1339-2dcgi 1 8 9 16 idt 1339c-31 sri #yyww**$ IDT1339c-31sri 1 8 9 16 idt 1339c-2 sri #yyww**$ IDT1339c-2sri
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 22 IDT1339 rev k 032910 package outline and package dimensions (8-pin soic, 150 mil. body) package dimensions are kept current with jedec publ ication no. 95 index area 1 2 8 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.33 0.51 .013 .020 c 0.19 0.25 .0075 .0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 l 0.40 1.27 .016 .050 0 8 0 8
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 23 IDT1339 rev k 032910 package outline and package dimensions (8-pin msop, 3.00 mm body) package dimensions are kept current with jedec publ ication no. 95 in d e x a r e a 1 2 8 d e 1 e s e a t in g p la n e a 1 a a 2 e - c - b a a a c c l *for reference only. controlling dimensions in mm. millimeters inches* symbol min max min max a -- 1.10 -- 0.043 a1 0 0.15 0 0.006 a2 0.79 0.97 0.031 0.038 b 0.22 0.38 0.008 0.015 c 0.08 0.23 0.003 0.009 d 3.00 basic 0.118 basic e 4.90 basic 0.193 basic e1 3.00 basic 0.118 basic e 0.65 basic 0.0256 basic l 0.40 0.80 0.016 0.032 0 8 0 8 aaa - 0.10 - 0.004
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 24 IDT1339 rev k 032910 package outline and package dimensions (16-pin soic, 300 mil body) package dimensions are kept current with jedec publ ication no. 95 index area 1 2 16 d e1 e seating plane a 1 a a 2 e - c - b aaa c c l *for reference only. controlling dimensions in mm. millimeters inches* symbol min max min max a -- 2.65 -- 0.104 a1 0.10 -- 0.0040 -- a2 2.05 2.55 0.081 0.100 b 0.33 0.51 0.013 0.020 c 0.18 0.32 0.007 0.013 d 10.10 10.50 0.397 0.413 e 10.00 10.65 0.394 0.419 e1 7.40 7.60 0.291 0.299 e 1.27 basic 0.050 basic l 0.40 1.27 0.016 0.050 0 8 0 8 aaa - 0.10 - 0.004
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 25 IDT1339 rev k 032910 ordering information the IDT1339 packages are rohs compliant. packages w ithout the integrated crystal are pb-free; packages that include the integrated crystal (as designated with a ?c? before the dash number) may include lead that is exempt u nder rohs requirements. the lead finish is jesd91 category e3 . while the information presented herein has been che cked for both accuracy and reliability, integrated device technology (idt) assumes no responsibility for either its use or for the inf ringement of any patents or other rights of third p arties, which would result from its use. no other circuits, patents, or licenses are implied. t his product is intended for use in normal commercia l applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environme ntal requirements are not recommended without additional processing by idt. i dt reserves the right to change any circuitry or sp ecifications without notice. idt does not authorize or warrant any idt product for u se in life support devices or critical medical inst ruments. part / order number marking shipping packaging package temperature 1339-2dvgi see page 20 tubes 8-pin msop -40 to +85 c 1339-2dvgi8 tape and reel 8-pin msop -40 to +85 c 1339-2dcgi tubes 8-pin soic -40 to +85 c 1339-2dcgi8 tape and reel 8-pin soic -40 to +85 c 1339c-2sri tubes 16-pin soic -40 to +85 c 1339c-2sri8 tape and reel 16-pin soic -40 to +85 c 1339-31dvgi tubes 8-pin msop -40 to +85 c 1339-31dvgi8 tape and reel 8-pin msop -40 to +85 c 1339-31dcgi tubes 8-pin soic -40 to +85 c 1339-31dcgi8 tape and reel 8-pin soic -40 to +85 c 1339c-31sri tubes 16-pin soic -40 to +85 c 1339c-31sri8 tape and reel 16-pin soic -40 to +85 c
IDT1339 real-time clock with serial i 2 c interface rtc idt? real-time clock with serial i 2 c interface 26 IDT1339 rev k 032910 revision history rev. originator date description of change a s. sharma 06/26/07 new device. preliminary release. b j. sarma 11/01/07 updated ordering info for 16-pin s oic package. c j. sarma 01/17/08 added 8-pin soic package; updated ?power-up/down characteristics? table; updates to ? absolute maximum ratings? table. d j. sarma 02/11/08 combined part numbers for 1339-3 a nd 1339-33 into one part number: 1339-31. e j.sarma 03/28/08 added new note to part ordering inf ormation pertaining to rohs compliance and pb-free devices. f j.sarma 05/18/08 changed the part number for the 16p in soic package from IDT1339c-31sogi to IDT1339c-31sri and the IDT1339c-2sogi changed to id t1339c-2sri g j.sarma 08/04/08 removed ?preliminary?; removed ul s tatement from pin 3 description. h j.sarma 11/20/08 updated block diagram, detailed des cription section(s), operating circuit diagram, and typical operating characteristics diagrams. i j.sarma 12/03/08 updated block diagram, features bul lets, pin descriptions, typical operating character istics diagrams; added marking diagrams. j 11/10/09 added ?handling, pcb layout, and assembly? section. k s.s. 03/29/10 added ?timeout? paragraph on page 11.
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